Current-controlled saw-tooth wave oscillator stage

ABSTRACT

This high-precision oscillator stage, with reduced response times, includes only NPN transistors on the signal path and comprises a threshold detector circuit connected to a first and to a second threshold voltage and to the output of the stage so as to generate a differential voltage output signal which switches when each voltage threshold is reached, a control and memory circuit comprising a differential voltage detector connected to the output of the threshold detector and generating a charge and discharge signal depending on the state of the circuit, a memory element controlled by the differential voltage detector to maintain the charge and discharge states and an output driving circuit connected to the control and memory circuit so as to supply an external capacitor with constant currents so as to alternately and periodically charge and discharge the capacitor.

BACKGROUND OF THE INVENTION

The present invention relates to a current-controlled saw-tooth waveoscillator stage of the type with unswitched thresholds, in particularfor high-definition television screens and monitors.

As is known, an oscillator stage capable of generating an appropriatesaw-tooth wave is currently used to drive the horizontal and verticaldeflection of monitors and television circuits. In particular,oscillators stages with markedly high performance in terms of operatingfrequency, temperature stability and output signal precision arerequired to drive high-definition television circuits and monitors.

For example, the integrated circuit illustrated in FIG. 1 is known forgenerating said driving signals. Said circuit constitutes acurrent-controlled oscillator and is capable of supplying a saw-toothvoltage V_(OUT) at the output indicated by 5; the oscillation frequencyof said voltage depends on the value of a resistive element R_(EXT) andof a capacitive element C_(EXT) which are normally external to theintegrated circuit and are respectively connected to the terminals 1 and2 thereof, as well as on the difference between two threshold values V₁and V₂ generated internally to the circuit. In detail, the outputvoltage V_(OUT) is obtained by charging and discharging the capacitorC_(EXT) between the two thresholds V₁ and V₂. For this purpose, theoscillator stage comprises a first section 10 including a resistivedivider for generating the threshold voltages and a buffer constitutedby a fedback amplifier with unitary gain capable of supplying areference voltage V_(REF) at the terminal 1 to which the resistorR_(EXT) is connected. This resistor connected between said terminal andthe ground thus allows to precisely set a reference current I which isthen appropriately mirrored so as to obtain stable current sources withvalues I/2 and 2I included in the driving section 12 of the actualsaw-tooth wave generator, which is indicated as a whole by the referencenumeral 11. Said saw-tooth wave generator furthermore comprises athreshold detector stage 13 connected at the input to the output V_(OUT)of the oscillator stage. The detector circuit 13, which is alsoconnected to the threshold voltages V₁ and V₂, defines a pair of outputs14 and 15 on which appropriate pulses are available respectively whenthe upper threshold voltage V₁ or the lower threshold voltage V₂ arereached. Said outputs 14 and 15 are connected to a pair of switchesindicated as a whole by 16 and respectively constituted by transistorsT₁₁ and T₁₂ intended to transfer said threshold-reaching pulses to aflip-flop stage 17 at the inputs S and R thereof. The outputs of saidflip-flop memory circuit 17 are sent to the bases of a differentialcircuit constituted by two transistors T₁ and T₂ belonging to thedriving stage 12, so as to alternately switch on the transistor T₂ andto switch off the transistor T₁ (thus allowing the capacitor to chargeat the constant current I/2) or to switch off transistor T₂ and toswitch on the transistor T₁ (thus allowing the capacitor to discharge atthe current 1.5I as an effect of the generators I/2 and 2I).

The capacitor is consequently discharged with a current three timeshigher than the charge current, thus creating a saw-tooth wave with arise time t_(c) equal to three times the fall time t_(d). The period Tof the resulting waveform can be easily calculated by means of theequation

    IΔt=CΔV

in which I is the charge or discharge current of the capacitor C in thetime Δt in the voltage range ΔV. In this case one thus obtains ##EQU1##wherein i_(c) =I/2 and i_(d) =1.5I.

In order to achieve this behavior the threshold detector circuit 13comprises two pairs of differential transistors T₇ -T₁₀ ; which, aspreviously mentioned, when the upper or lower threshold is reached, senda reset or set pulse respectively at the output 14 or at the output 15,respectively to the base R of T₆ or to the base S of T₃ so as toalternately cause the transistors T₁ and T₂ to conduct, as previouslyexplained.

It should be furthermore noted that, since the output signal V_(OUT)must be available to the stages connected downstream for the subsequentprocessings, there is a buffer stage B which decouples it from thesignal present on the terminal 2, thus avoiding "loading" effects whichcan alter the preset values of the charge and discharge currents (signaldeformation).

The above described stage operates advantageously as to its flexibility,since the set current can be varied within a wide range through R_(EXT)(which does not depend on the temperature), and because switchthresholds not depending on variable parameters but on integratedresistive dividers are available and the dynamics of the output signal(defined as the ratio between the charge time and the discharge time)can be varied within a wide range by varying the currents i_(c) andi_(d).

However, the described circuit is not suitable for drivinghigh-definition television circuits and monitors. Said circuit is infact incapable of providing the response rapidity and the precisionrequired for this type of application due to the presence of PNPtransistors (such as T₁₁ and T₁₂) and of saturating elements (i.e. thetransistors T₃ -T₆ of the flip-flop stage 17) on the signal path. Thepresence of these transistors limits the operating frequency of thestage, slowing the response time of the entire system, with the doubleeffect of preventing the circuit from oscillating at high frequenciesand of introducing an error on the peak values of the output signal withrespect to the values of the preset thresholds. Said error isfurthermore not fixed but depends on the temperature, which as is knowninfluences the response times of transistors, causing the drift of theoperating frequency with respect to its nominal value.

SUMMARY OF THE INVENTION

Given this situation, the aim of the present invention is to provide asaw-tooth wave oscillator stage of the indicated type, capable thereforeof ensuring the flexibility and dynamics levels typical of the knowncircuit while at the same time overcoming its disadvantages.

Within this aim, a particular object of the present invention is toprovide an oscillator stage which operates without saturating elementsand without PNP-type transistors on the signal path, thus obtaining ahigh operating frequency of the stage.

Another particular object of the present invention is to provide anoscillator stage having practically negligible response times andtherefore high temperature stability.

Still another object of the present invention is to provide anoscillator stage with high precision which switches exactly at thepreset thresholds.

Not least object of the present invention is to provide an oscillatorstage having an electrically simple structure which can be easilyintegrated and therefore implemented with modest costs.

This aim, these objects and others which will become apparenthereinafter are achieved by a saw-tooth wave oscillator stage as definedin the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The characteristics and advantages of the oscillator stage according tothe invention will become apparent from the description of a preferredbut not exclusive embodiment, illustrated only by way of non-limitativeexample in the accompanying drawings, wherein:

FIG. 1 is the electric circuit diagram of a known oscillator stage;

FIGS. 2a and 2b illustrate voltage signals obtainable by the oscillatorstage according to the invention; and

FIG. 3 is an electric circuit diagram of the oscillator stage accordingto the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is not described hereinafter: reference is made to theintroduction of the present description for said figure.

Reference is thus made to FIG. 3, illustrating the diagram of theoscillator stage according to the invention. In this diagram the partswhich are equivalent or identical to the known oscillator circuit areindicated by the same reference numerals. In particular, the stage 10for generating the reference and threshold currents and voltages is onlypartially illustrated, since it is entirely identical to the known oneof FIG. 1. As regards the actual saw-tooth wave generator circuit 11,said circuit is again composed of a driving stage or circuit 12 and of athreshold detector circuit 13', but the control and memory circuit,which previously comprised the switches 16 and the flip-flop 17, is nowindicated by 18. Similarly to the known oscillator stage, the drivingcircuit 12 comprises a pair of transistors T₁ and T₂ connected indifferential configuration so as to alternately feed the capacitorC_(EXT) with the charge current supplied by the generator I/2 or allowthe controlled discharge of the capacitor at the current 1.5I. Theterminal 2 connected to the capacitor C_(EXT) is then connected, throughthe buffer B, to the output 5 feeding voltage V_(OUT) and to an input ofthe threshold detector circuit 13', constituted here, too, by a pair ofdifferential circuits formed by the transistors T₂₀ -T₂₃. In detail, thebase of T₂₀ is connected to the output of the oscillator stage, whilethe base of T₂₁ is connected to the upper voltage reference V₁, theiremitters are connected to one another and to a constant-current sourceswith a value of 3/2 I_(S), and the collector of T₂₁ is connected to thepower supply V_(CC) while the collector of T₂₀ defines an output 14 ofthe threshold circuit. In the circuit according to the invention, T₂₀and T₂₁ are implemented so that the former has twice the area of thelatter, so that when the differential circuit is balanced with theoutput V_(OUT) at the upper threshold voltage, T₂₀ conducts twice thecurrent of T₂₁. Similarly, in the lower differential circuit, the baseof T₂₂ is connected to the output V_(OUT), while the base of T₂₃ isconnected to the lower voltage reference V₂, the emitters of the twotransistors are connected to one another and to a constant-currentsource 3/2 I_(S), the collector of T₂₂ is connected to the supplyvoltage while the collector of T₂₃ defines the output 15. Similarly tothe upper differential, the area of T₂₃ is twice that of T₂₂. Thecollector of T₂₀ and the collector of T₂₃ are furthermore connected tothe supply voltage V_(CC) by means of respective resistors R₁ and R₂ ofequal value.

According to the invention, the control and memory circuit 18 nowcomprises a detector of the differential voltage existing between theoutputs 14 and 15 of the threshold circuit 13' and by a differentialcircuit acting as memory, controlled by circuit 13' and connected inparallel to the circuit 12. In detail, the differential voltage detectorcomprises a pair of transistors T₂₄ and T₂₅ and by resistors R₃ -R₅. Thetransistor T₂₄ has its base terminal connected to the output 14 and itscollector terminal connected to the power supply, while its emitter isconnected to R₄ ; T₂₅ has its base connected to the output 15, itscollector connected to the power supply and its emitter connected to theresistor R₃. As can be seen, both transistors T₂₄ and T₂₅ are of the NPNtype. In turn the resistors R₃ and R₄ are connected to the two terminalsof R₅ at the points indicated by A and B connected to the bases of T₁and T₂ respectively. Constant reference current sources I_(R), arefurthermore connected to the points A and B. In turn, the memoryelement, which confirms the charge or discharge state of the capacitorstarted by means of the differential voltage detector circuit, comprisesthe transistors T₂₆ and T₂₇, also of the NPN type, connected in adifferential arrangement and precisely with their bases respectivelyconnected to point A and to point B, their collectors respectivelyconnected to the output 14 and the output 15, and their emittersconnected to one another and to the constant-current source I_(S) /2.

The oscillator stage according to the invention operates as follows.Similarly to the known circuit, when the voltage at point A is lowerthan that at point B the transistor T₁ is off and the external capacitoris charged in a linear manner by the current I/2, following the risingline shown in FIG. 2A. During this step the voltage V_(OUT) is at anintermediate value between the two thresholds, so that the transistorsT₂₁, T₂₂ and T₂₇ are on while the transistors T₂₀, T₂₃ and T₂₆ are off.In this condition, the base of T₂₄ is approximately biased to the supplyvoltage V_(CC) (ignoring the small drop on the resistor R₁ due to thebase current of T₂₄), while the base of T₂₅ is biased to the voltageV_(CC) -R₂ I_(S) /2.

The differential signal present between the outputs 14 and 15 (i.e.between the bases of T₂₄ and T₂₅) and therefore between the emitters ofsaid transistors is thus equal to R₂ I_(S) /2, causing a voltage dropacross the resistor R₅ equal to ##EQU2## since the path of the signalaffects exclusively the transistors T₂₄, T₂₅ and the resistors R₃ -R₅.

A signal current I_(X) thus flows across the resistor R₅ from point B topoint A with a value equal to (V_(B) -V_(A))/R₅, so that if the basecurrents of T₂₇ and T₂₆ are ignored the transistor T₂₄ conducts thecurrent I_(R) '+I_(X) while the transistor T₂₅ conducts the currentI_(R) '-I_(X).

When the output voltage V_(OUT) (and therefore the voltage on the baseof T₂₀) reaches the upper threshold value V₁ the transistor T₂₀ conductsthe current I_(S) since the differential circuit T₂₀, T₂₁ is balancedand, due to the area ratio, T₂₀ conducts twice the current of T₂₁. Avoltage drop equal to R₁ I_(S) thus occurs across R₁, while a voltageequal to R₂ I_(S) /2 is still present across R₂. This causes a reversalof the differential signal present between the outputs 14 and 15 andtherefore between the emitters of T₂₄ and T₂₅, which reversal in turnentails a reversal in the flow direction of the current I_(X) flowingacross the resistor R₅. T₂₄ consequently now conducts a current equal toI_(R) '-I_(X) while T₂₅ conducts a current equal to I_(R) '+I_(X).

The voltage at point A is consequently higher than the voltage of pointB, causing the differential circuit T₂₆, T₂₇ to switch. Therefore, inthis operation state T₂₆ and T₁ switch on while T₂₇ and T₂ switch off,thus starting the discharge of the capacitor C_(EXT) at the current1.5I. The start of the discharge state also causes switching off of T₂₀; its switching off however entails no problems, since the switching onof T₂₆ has meanwhile already confirmed the threshold crossing condition.

During discharge the situation is similar and complementary to the onealready described during charging. In particular, during this phase thetransistors T₂₁, T₂₂, T₂₆ and T₁ are on, T₂₀, T₂₃, T₂₇ and T₂ are off,the base of T₂₄ is biased at the voltage V_(CC) -R₁ I_(S) /2 and thebase of T₂₅ is practically at the supply voltage.

Finally, when the output signal V_(OUT) reaches the lower threshold V₂,T₂₃ conducts the current I_(S) and therefore causes a pulse at the baseof T₂₅ which again unbalances the differential circuits T₂₆ and T₂₇, T₁and T₂. When the charging of the external capacitor again resumes, theconduction of T₂₇ stores the information that the threshold has beenreached, confirming the charging condition of the capacitor and thusobtaining the signal shown in FIG. 2A. In practice, the differentialcircuit T₂₆, T₂₇ acts as state memory, thus implementing the functionperformed by the flip-flop in the known circuit.

It should be furthermore noted that the circuit can also provide at theoutput a square wave at the collector of T₂ (open collector), saidsquare wave having the same dutycycle as the saw-tooth wave signalsupplied at the output and shown in FIG. 2b.

As can be seen from the preceding description, the invention fullyachieves the proposed aim and objects. The oscillator stage according tothe invention is in fact capable of generating the required saw-toothwave without using PNP or saturating transistors on the signal path. Theoscillator stage according to the invention is therefore capable ofoperating even at high frequencies, higher than those obtainable withthe known circuit.

The described circuit furthermore has high temperature stability, sincethe response times of the system (which are a function of thetemperature) are practically negligible as PNP transistors, which areslower than NPN ones, have been eliminated.

The rapid response of the system furthermore entails high precision alsoby virtue of the fact that the switching thresholds are linked tointegrated resistive dividers. This high precision is also obtained byvirtue of the fact that the transistors of the differential circuits ofthe threshold detector circuit have an appropriate area ratio, asindicated, and thus conduct the current required to switch the memoryelement already during the balancing of one of the differential circuitsof the threshold detector. The illustrated solution is furthermorecircuitally simple and easy to integrate, entailing reducedmanufacturing costs.

Finally, the fact is stressed that the circuit according to theinvention allows to achieve the above described aims without having torenounce the advantages already featured by known structures such as thepossibility to vary the operating frequency and the dynamics of theoutput signal within a wide range, furthermore providing at the output asquare-wave signal with the same duty-cycle as the required saw-toothsignal.

The invention thus conceived is susceptible to numerous modificationsand variations, all of which are within the scope of the inventiveconcept. In particular all the circuit elements may be replaced withother technically equivalent ones capable of performing the samefunctions.

I claim:
 1. A saw-tooth wave oscillator stage having an output terminalfeeding a drive signal for driving a capacitive element to bealternately and periodically brought in a charge and in a dischargestate and generating an output signal, said stage comprising:a first anda second, upper and lower, threshold voltages, a threshold detectorcircuit connected to said first and second threshold voltages and tosaid output terminal and having a pair of detector circuit outputsdefining a differential voltage switching between a positive and anegative sign when said output signal reaches said first and secondthresholds, a control and memory circuit connected to said detectorcircuit outputs for generating a differential charge and dischargesignal alternately and periodically having charge and discharge phases,and an output driving circuit receiving said charge and discharge signaland generating said drive signal, wherein said control and memorycircuit comprises a differential voltage detector connected between saiddetector circuit outputs for detecting switching of said sign of saiddifferential voltage and for correspondingly switching said differentialcharge and discharge signal between said charge and discharge phases,and a memory element controlled by said differential voltage detectorand connected to said driving circuit for maintaining said charge anddischarge phases until subsequent switching of said differentialvoltage.
 2. A stage according to claim 1, wherein said differentialvoltage detector comprises a pair of transistors having emitter, baseand collector terminals, said base terminals being connected to arespective one of said detector circuit outputs and said emitterterminals being mutually connected through at least one resistiveelement generating said differential charge and discharge signal.
 3. Astage according to claim 1, wherein said memory element comprises adifferential circuit including a pair of transistors having emitter,base and collector terminals, said emitter terminals being mutuallycoupled and connected to a current source, said collector terminalsbeing connected to a respective one of said detector circuit outputs andsaid base terminals connected to said differential voltage detector. 4.A stage according to claim 1, wherein said threshold detector circuitcomprises two differential stages each including a first transistor anda second transistor having coupled emitter terminals, said firsttransistor of said first differential stage having a base terminalconnected to said output terminal and a collector terminal forming afirst output of said threshold detector circuit, said second transistorof said first differential stage having a base terminal connected tosaid first threshold voltage, said first transistor of said seconddifferential stage having a base terminal connected to said outputterminal and said second transistor of said second differential stagehaving a base terminal connected to said second threshold voltage and acollector terminal forming the second output of said threshold detectorcircuit, said first transistor of said first differential stage and saidsecond transistor of said second differential stage having an area whichis a multiple of an area of said second transistor of said firstdifferential stage and of said first transistor of said seconddifferential stage.
 5. A stage according to claim 4, wherein the areasof said first transistor of said first differential stage and of saidsecond transistor of said second differential stage are twice the areasof said second transistor of said first differential stage and of saidfirst transistor of said second differential stage.
 6. A stage accordingto claim 1, wherein said memory element comprises a first differentialcircuit including a first pair of transistors having mutually coupledemitter terminals which are connected to a constant current sourcefeeding a first constant current and said threshold detector circuitcomprises two further differential stages each including first andsecond transistors having emitter terminals, said emitter terminals ofsaid transistors of each of said further differential stages beingmutually coupled and being connected to a further current source feedinga second constant current which is three times higher than said firstconstant current.
 7. A stage according claim 2, wherein said detectorcircuit outputs are connected to a supply voltage through respectivesubstantially equal resistors and said emitter terminals of said pair oftransistors of said differential voltage detector are connected to saidresistive element through further respective equal resistors.
 8. A stageaccording to claim 1, wherein said threshold detector circuit, saiddifferential voltage detector and said memory element comprisedifferential circuits including transistors of the NPN type.